Memory devices such as static random access memories comprise an array of individual memory cells. Typically, a static RAM cell consists of a basic bistable flip-flop circuit which needs only a DC current applied to retain its memory. A SRAM allows the user both to read information from the memory and to write new information into the memory. Data is read from memory by activating a row, referred to as a word line, which couples all memory cells corresponding to that row to active digit or bit lines which define the columns of the array. When a particular word line is activated, sense amplifiers connected to active bit lines detect and amplify the data by measuring the potential difference between the activated bit lines.
A standard SRAM cell 10 is shown in FIG. 1. Cell 10 consists of four transistors 14, 16, 20 and 22, and two control transistors 12 and 18. Data is stored with either a high potential at node A and a low potential at node B, or a low potential at node A and a high potential at node B. This means that two stable states are available which are defined as a logic `1` or a logic `0`.
Cell 10 is embedded in an array of similar cells as shown in FIG. 2. A typical RAM consists of a matrix of storage bits with bit capacity 2.sup.N .times.2.sup.M bits arranged in an array 100 with 2.sup.M columns (bit lines) and 2.sup.N rows (word lines).
To read data stored in the array, a row address is input and decoded by row decoder 102 to select one of the rows or word lines. All of the cells along this word line are activated. Column decoder 104 then addresses one bit out of the 2.sup.M bits that have been activated and routes the data that is stored in that bit to a sense amplifier (not shown) and then out of the array. Data in and Data out are controlled by the Read/Write Control circuit 106.
The logic state of SRAM cell 10 of FIG. 1, i.e. either a `1` or `0`, is read by sensing the cell current on bit line pair comprised of bitlines 30 and 32 and/or the differential voltage developed thereon. When wordline 40 is selected, cell 10 is activated by turning on transistors 12 and 18. If the activated SRAM cell is in logic state `1` node A is high and node B is low. Transistor 14 will be off, transistor 16 will be on, transistor 20 will be on, and transistor 22 will be off. Since transistors 16 and 18 are on, bit line 32 will carry cell current, while bit line 30 will not carry any cell current since transistor 14 is off.
The logic state `0` would be the opposite with node A low and node B high. Transistor 14 will be on, transistor 16 will be off, transistor 20 will be off, and transistor 22 will be on. Bit line 30 will carry cell current, while bit line 32 will not carry cell current.
FIG. 3 illustrates how a sense amplifier is differentially connected to a complementary pair of bit lines, e.g. 30, 32, for sensing the state of an addressed cell. The cell current carried by one of the bit lines 30 or 32 will cause a voltage drop on that bit line. This voltage drop may be caused by the cell current acting on the bit line capacitances 110 or 111 (FIG. 3), or the corresponding voltage drop on the bit line loads 115 or 116. The voltage drop on the bit line carrying the cell current creates a voltage differential between bit line 30 and bit line 32, called the bit line spread. Bit lines 30 and 32 are input to sense amplifier 120. Sense amplifier 120 reads the differential input of the bit line spread to determine the stored logic state of cell 10. A signal representing the stored logic state of cell 10 is output from sense amplifier 120 on data line 122.
A major disadvantage of a static RAM is that it is volatile, that is, it will lose its memory if the power is turned off. It is important in many memory system environments that the memory contents be retained when the power is off.
A Read Only Memory (ROM) is non-volatile, that is, it retains its memory when the power is turned off. A ROM cell is a transistor which is effectively either present or absent at a given location in the memory. A ROM is the best memory solution where a fixed program is being stored, such as in gaming machines, language character generators, and operating system storage in computer systems.
A Programmable ROM (PROM) is preprogrammed in the silicon by the memory manufacturer. An Erasable PROM (EPROM) can be erased and reprogrammed by the user utilizing ultraviolet light which enters the memory package through a quartz window. An Electrically Erasable PROM (EEPROM) can be erased electrically, eliminating the need to remove the memory chip from the system and the purchase of expensive ultraviolet light equipment as is needed with an EPROM. A One Time Programmable ROM (OTPROM) can be programmed only once and cannot be changed.
ROMs are typically manufacturer customized parts which are basically limited to market segments and applications with a predefined and relatively long term data storage use. The need for a non-volatile memory often occurs in small volume applications or in applications where the software is undergoing constant updating in order to remain current in a competitive market situation. In many cases, the initial programming cost and minimum volume requirements can make ROMs prohibitively expensive. Thus, the problem exists of providing ROM in a cost effective manner while utilizing existing support circuitry.